1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a voltage generator for a semiconductor device.
2. Background of the Related Art
FIG. 1 illustrates an example of a conventional high voltage generating circuit described in U.S. Pat. No. 5,818,289. As illustrated therein, the conventional high voltage generating circuit includes oscillator 10, clock signal generator 12, pump circuit 14 and regulator 16.
The oscillator 10 generates oscillation signal OSC used to trigger the operation of the clock signal generator 12, and often is a ring oscillator initiated by enable signal EN. The clock signal generator 12 is triggered by the oscillation signal OSC to generate the clock signals used to control the operation of the pump circuit 14. The pump circuit 14 is composed of multi stage charge pumps. The pump circuit 14 outputs the higher voltages needed for programming and erasing memory cells by performing a pumping operation according to the clock signals outputted from clock signal generator 12.
The regulator 16 outputs reset signal RST used to turn the oscillator 10 off when the pump circuit 14 outputs the appropriate voltage. That is, the regulator 16 is used to control the operation of the oscillator 10 in order to cause the output of the pump circuit 14 to approach the desired output voltage. Thus, the oscillator 10 is turned on or off by the regulator 16, which in turn affects the frequency of the clock signals produced by the clock signal generator 12, to obtain the desired higher voltages from the pump circuit 14.
FIG. 2 is a circuit diagram of the clock signal generator 12. As illustrated in FIG. 2, flip-flop 220 outputs clock signals Ph0 and Ph0# by dividing the oscillator signal OSC by two, and is reset by the reset signal RST. A plurality of logic gates are used to produce the desired clock signals (Ph1#, Ph2#, Ph3, Ph1a, and Ph2a) that control the operation of the pump circuit 14 upon receipt of the oscillation signal OSC and/or the output of the flip-flop 220. Namely, inverters 231 and 232 provide the delays of the oscillation signal OSC that produce signal OSC-T.
NAND gate 234 and inverter 236 are used to produce clock signal Ph1 by using signals Ph0 and OSC-T. NAND gate 244 and inverter 246 are used to produce clock signal Ph2 by using signals Ph0# and OSC-T. The clock signal Ph1 is inverted by inverter 238 to produce clock signal Ph1#, and the clock signal Ph2 is inverted by inverter 248 to produce clock signal Ph2#.
Inverters 240 and 242 are used to provide a delayed version of signal Ph1, which produces clock signal Ph1d, and inverters 250 and 252 are used to provide a delayed version of signal Ph2, which produces clock signal Ph2d. In addition, NOR gate 254 produces clock signal Ph3 by NORing the oscillation signal OSC and the clock signals Ph1d and Ph2d. NAND gate 256 and inverter 258 produce clock signal Ph1a by using the oscillation signal OSC and the clock signal Ph1d, and NAND gate 260 and inverter 262 produce clock signal Ph2a by using the oscillation signal OSC and the clock signal Ph2d. 
FIG. 3 illustrates a circuit diagram of the pump circuit 14 controlled by clock signals (Ph1#, Ph2#, Ph3, Ph1a, and Ph2a). As illustrated in FIG. 3, the pump circuit 14 includes first and second pump stages 160 and 170 connected by charge transfer switch 80. The input to first pump stage 160 may be either an input power supply voltage or the output from a previous pump stage. The output from second pump stage 170 provides the input to the next stage, or to an output stage if second pump stage 170 is the last in the charge pump.
The first pump stage 160 is composed of a switching transistor 60, a capacitor 62, a transistor 64 configured to act as a diode when the transistor 60 is switched xe2x80x9con,xe2x80x9d and a pump capacitor 66. Capacitors 68 and 69 represents the parasitic capacitance on the clock driver side associated with pump capacitors 66 and 67, respectively, and capacitors 70 and 71 represents the parasitic capacitance on the charged nodes St1 and St2, respectively.
Transistors 72 and 74 are used as clock drivers, and power supply voltage line 54 is used as the power source for transistors 74 and 75. If the first pump stage is the first stage in the charge pump, the input supply voltage and the voltage of power supply line 54 are identical, that is, a VDD level. In addition, since the configuration of the second pump stage is the same as the first pump stage St1 except for reference numerals, the detailed description thereof is omitted.
The operation of the pump circuit 14 will now be described using waveforms shown in FIG. 4. At time t1, the clock signal Ph1# goes low, turning on the transistor 74 and thereby charging node S1P to the voltage level VDD of the power supply voltage line 54. When node S1P is charged to the VDD level, the voltage of the node St1 is increased by the pumping operation of the pump capacitor 66 and turns on the switching transistor 60. As the result, node VG1 is charged to an input supply voltage level through the turned-on switching transistor 60. At time t2, the clock signal Ph1a goes high, turning on the transistor 73 and thereby pulling node S2P down to a ground level.
At time t3, the clock signal Ph1# goes high, causing the transistor 74 to disconnect the node S1P from the power supply voltage line 54. Soon after, the clock signal Ph3 goes high, which causes charge transfer switch 80 to be turned on and connect the node S1P to the node S2P. Thus, for the next charging cycle, charge is transferred from the node S1P to the node S2P (i.e. from parasitic capacitor 68 to parasitic capacitor 69). The amount of charge transferred will be one-half that stored in the capacitor 68. Shortly prior to time t4, clock signal Ph3 goes low to disconnect the node SIP from the node S2P.
At time t4, the clock signal Ph2# goes low, charging the node S2P to the power supply voltage. Thus, the switching transistor 61 is turned on according to the voltage of the node St2 using the pumping operation of the pump capacitor 67.
At time t5, the clock signal Ph2a goes high, discharging the charge of the node S1P to the ground side through the transistor 72, and increasing the voltage of the node VG1 to an input supply voltage or more by means of the pumping operation of the capacitor 62. As the result, the switching transistor 65 is turned on by the increased voltage of the node VG1, thereby providing the node St1 and the node VG2 with an input supply voltage without the threshold voltage drop.
At time t6, the clock signal Ph2# goes high, disconnecting the node S2P from the power supply voltage line 54. Shortly after time t6, the clock signal Ph3 goes high, turning on charge transfer transistor 80 and thereby connecting the node S1P to the node S2P. This has the effect of transferring charge from the node S2P to the node S1P (i.e. from capacitor 69 to capacitor 68).
Shortly before time t7, the clock signal Ph3 goes low again, disconnecting the node S1P from the node S2P. At time t7, the clock signal Ph1# goes low, connecting the node S1P to power supply voltage line 54 by means of transistor 74. Thus, the voltage of node St1 is pumped up to the level of an input supply voltage or more. Soon after time t7, the clock signal Ph1a goes high, turning on the switching transistor 65 by the pumping of the capacitor 63 and thereby transferring the voltage of the node St1a to the node St2. The voltage of the node St2 is pumped by the pump capacitor 67 to be outputted using output transistor 77, when the clock signal Ph2# goes high again.
In this way, in the conventional high voltage generating circuit, the charge stored in the parasitic capacitor 68 (or 69) is transferred to the parasitic capacitor 69 (or 68) through the charge transfer switch 80 to achieve the charge sharing.
However, as described above, the conventional high voltage generating circuit has various disadvantages. The pump circuit needs a predetermined charge sharing time for pre-charging and discharging the parasitic capacitors of two pump stages, which reduces or degrades the operational speed. Further, the charge sharing occurs in the conventional pump circuit only between the two pump stages. Thus, in the case of pump circuit composed of three pump stages, the charge sharing effect is decreased. In addition, in the conventional pump circuit, diode-type transistor 77 is used to prevent the reversal of current at an output stage, reducing or degrading a voltage of the output stage using the diode-type transistor 77. In the conventional high voltage generating circuit, the pumping efficiency is degraded because of the above-described disadvantages.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a voltage generator that reduces power consumption.
Another object of the present invention is to provide a voltage generator that reduces chip area.
Another object of the present invention is to provide a high voltage generating circuit that is capable of reducing power consumption and a chip area.
Another object of the present invention is to provide a charge pump circuit appropriate for a low power chip.
Another object of the present invention is to provide a charge pump circuit appropriate for a low power chip by increasing the pumping efficiency.
To achieve the above objects, there is provided a voltage generator according to the present invention that includes a clock signal generator that generates a plurality of clock signals upon receipt of an oscillation signal, a high voltage clock generator that generates a plurality of high voltage clock signals upon receipt of a clock signal from the clock signal generator, and a pump circuit that alternately performs pumping and pre-charging operations according to the clock signals and the high voltage clock signals from the clock signal generator and the high voltage clock generator, respectively, to output a pumping voltage.
To further achieve the above objects, there is provided a pump circuit in accordance with the present invention that includes first and second pump stages that each alternately perform stage pumping and stage pre-charging operations according to selected ones of a plurality of first clock signals and a plurality of second clock signals, and a pre-charge stage that pre-charges the first pump stage to a power supply level according to one of the second clock signals, wherein each of the pump stages includes first and second pumps with a symmetrical structure, each having a pumping capacitor that alternately performs one of the stage pumping and the stage pre-charging operations during a first clock cycle of the pump circuit, and a charge transfer switch coupled between the pumping capacitors of the first and second pumps to transfer the charge of the pumping capacitor having performed the stage pumping operation to the pumping capacitor having performed the stage pre-charging operation before the first clock cycle of the pump circuit is completed.
To further achieve the above objects, there is provided a voltage generator according to the present invention that includes clock generator means for generating a plurality of clock signals upon receipt of an oscillation signal from an oscillating means, high voltage clock generator for generating a plurality of high voltage clock signals upon receipt of a clock signal, and pump circuit means for alternately performing pumping and pre-charging operations according to the clock signals and the high voltage clock signals from the clock generator means and the high voltage clock generator means, respectively, to output a pumping voltage.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.